#ifndef REG_SYSC_AWO_TYPE_H_
#define REG_SYSC_AWO_TYPE_H_
#include <stdint.h>

typedef struct
{
    volatile uint32_t LOCK;
    volatile uint32_t OE_DOT;
    volatile uint32_t PUPD;
    volatile uint32_t IE_OD;
    volatile uint32_t DS;
    volatile uint32_t AE;
    volatile uint32_t FIR;
    volatile uint32_t DIN;
}awo_io_reg_t;

typedef struct
{
    volatile uint32_t RESERVED0[2];  //0x0 0x4
    volatile uint32_t CRYPT_WORD;       // 0x8
    volatile uint32_t AWO_CTRL;         // 0xc
    volatile uint32_t PWR_CTRL0;        // 0x10
    volatile uint32_t PWR_CTRL1;        // 0x14
    volatile uint32_t PWR_CTRL2;        // 0x18
    volatile uint32_t PWR_CTRL3;        // 0x1c
    volatile uint32_t RESERVED1[2];     // 0x20 0x24
    volatile uint32_t PD_AWO_CLKG_SRST; // 0x28
    volatile uint32_t PD_AWO_CLK_CTRL;  // 0x2c
    volatile uint32_t PD_AWO_ANA2;      // 0x30
    volatile uint32_t PD_AWO_ANA0;      // 0x34
    volatile uint32_t PD_AWO_ANA1;      // 0x38
    volatile uint32_t MAC_SLP_INTR;     // 0x3c
    volatile uint32_t PIN_SEL0;         // 0x40
    volatile uint32_t PIN_SEL1;         // 0x44
    volatile uint32_t PIN_SEL2;         // 0x48
    volatile uint32_t PIN_SEL3;         // 0x4c
    volatile uint32_t RESERVED2[4];     // 0x50 0x54 0x58 0x5c
    awo_io_reg_t IO[3];                 // 0x60
    volatile uint32_t PWR_ACK;
    volatile uint32_t DBG_ACK;
    volatile uint32_t ANA_STAT;
}reg_sysc_awo_t;

enum SYSC_AWO_REG_AWO_CTRL_FIELD
{
    SYSC_AWO_CRYPT_EN_MASK = (int)0x80000000,
    SYSC_AWO_CRYPT_EN_POS = 31,
    SYSC_AWO_AWO_CFG_HSICAL_MASK = (int)0x7fff,
    SYSC_AWO_AWO_CFG_HSICAL_POS = 0,
};

enum SYSC_AWO_REG_PWR_CTRL0_FIELD
{
    SYSC_AWO_PD_EN_SEC_MASK = (int)0x1,
    SYSC_AWO_PD_EN_SEC_POS = 0,
    SYSC_AWO_PD_EN_BLE_MASK = (int)0x2,
    SYSC_AWO_PD_EN_BLE_POS = 1,
    SYSC_AWO_PD_EN_PER_MASK = (int)0x4,
    SYSC_AWO_PD_EN_PER_POS = 2,
    SYSC_AWO_PD_EN_SRAM_MASK = (int)0x3f0,
    SYSC_AWO_PD_EN_SRAM_POS = 4,
    SYSC_AWO_PU_EN_SEC_MASK = (int)0x10000,
    SYSC_AWO_PU_EN_SEC_POS = 16,
    SYSC_AWO_PU_EN_BLE_MASK = (int)0x20000,
    SYSC_AWO_PU_EN_BLE_POS = 17,
    SYSC_AWO_PU_EN_PER_MASK = (int)0x40000,
    SYSC_AWO_PU_EN_PER_POS = 18,
    SYSC_AWO_PU_EN_SRAM_MASK = (int)0x3f00000,
    SYSC_AWO_PU_EN_SRAM_POS = 20,
};

enum SYSC_AWO_REG_PWR_CTRL1_FIELD
{
    SYSC_AWO_CLK_CLS_SET_MASK = (int)0x1,
    SYSC_AWO_CLK_CLS_SET_POS = 0,
    SYSC_AWO_CLK_CLS_CLR_MASK = (int)0x2,
    SYSC_AWO_CLK_CLS_CLR_POS = 1,
    SYSC_AWO_RST_ACT_SET_MASK = (int)0x4,
    SYSC_AWO_RST_ACT_SET_POS = 2,
    SYSC_AWO_RST_ACT_CLR_MASK = (int)0x8,
    SYSC_AWO_RST_ACT_CLR_POS = 3,
    SYSC_AWO_ISO_EN_SET_MASK = (int)0x10,
    SYSC_AWO_ISO_EN_SET_POS = 4,
    SYSC_AWO_ISO_EN_CLR_MASK = (int)0x20,
    SYSC_AWO_ISO_EN_CLR_POS = 5,
    SYSC_AWO_PWR_OFF_SET_MASK = (int)0x40,
    SYSC_AWO_PWR_OFF_SET_POS = 6,
    SYSC_AWO_PWR_OFF_CLR_MASK = (int)0x80,
    SYSC_AWO_PWR_OFF_CLR_POS = 7,
};

enum SYSC_AWO_REG_PWR_CTRL2_FIELD
{
    SYSC_AWO_PD_SRAM_DS_EN_MASK = (int)0x1,
    SYSC_AWO_PD_SRAM_DS_EN_POS = 0,
    SYSC_AWO_PMU_CLK_DLY_MASK = (int)0x3f0,
    SYSC_AWO_PMU_CLK_DLY_POS = 4,
    SYSC_AWO_PMU_FSM_DLY_MASK = (int)0xf000,
    SYSC_AWO_PMU_FSM_DLY_POS = 12,
    SYSC_AWO_PWR_SW_STB_MASK = (int)0x7f0000,
    SYSC_AWO_PWR_SW_STB_POS = 16,
    SYSC_AWO_MEM_DS_STB_MASK = (int)0x70000000,
    SYSC_AWO_MEM_DS_STB_POS = 28,
};

enum SYSC_AWO_REG_PWR_CTRL3_FIELD
{
    SYSC_AWO_V33_SLP_EN_MASK = (int)0x1,
    SYSC_AWO_V33_SLP_EN_POS = 0,
    SYSC_AWO_MODE_CLK_ONLY_MASK = (int)0x10,
    SYSC_AWO_MODE_CLK_ONLY_POS = 4,
};

enum SYSC_AWO_REG_PD_AWO_CLKG_SRST_FIELD
{
    SYSC_AWO_CLKG_SET_DIV_HBUS_MASK = (int)0x1,
    SYSC_AWO_CLKG_SET_DIV_HBUS_POS = 0,
    SYSC_AWO_CLKG_CLR_DIV_HBUS_MASK = (int)0x2,
    SYSC_AWO_CLKG_CLR_DIV_HBUS_POS = 1,
    SYSC_AWO_CLKG_SET_MAC_SLP_MASK = (int)0x4,
    SYSC_AWO_CLKG_SET_MAC_SLP_POS = 2,
    SYSC_AWO_CLKG_CLR_MAC_SLP_MASK = (int)0x8,
    SYSC_AWO_CLKG_CLR_MAC_SLP_POS = 3,
    SYSC_AWO_CLKG_SET_PMU_MASK = (int)0x10,
    SYSC_AWO_CLKG_SET_PMU_POS = 4,
    SYSC_AWO_CLKG_CLR_PMU_MASK = (int)0x20,
    SYSC_AWO_CLKG_CLR_PMU_POS = 5,
    SYSC_AWO_SRST_SET_MAC_SLP_N_MASK = (int)0x40,
    SYSC_AWO_SRST_SET_MAC_SLP_N_POS = 6,
    SYSC_AWO_SRST_CLR_MAC_SLP_N_MASK = (int)0x80,
    SYSC_AWO_SRST_CLR_MAC_SLP_N_POS = 7,
};

enum SYSC_AWO_REG_PD_AWO_CLK_CTRL_FIELD
{
    SYSC_AWO_CLK_DIV_PARA_HBUS_M1_MASK = (int)0xf,
    SYSC_AWO_CLK_DIV_PARA_HBUS_M1_POS = 0,
    SYSC_AWO_CLK_SEL_HBUS_L0_MASK = (int)0x70,
    SYSC_AWO_CLK_SEL_HBUS_L0_POS = 4,
    SYSC_AWO_CLK_SEL_HBUS_L1_MASK = (int)0x700,
    SYSC_AWO_CLK_SEL_HBUS_L1_POS = 8,
    SYSC_AWO_CLK_SEL_LS_MASK = (int)0x30000,
    SYSC_AWO_CLK_SEL_LS_POS = 16,
    SYSC_AWO_CLK_SEL_PBUS0_MASK = (int)0x100000,
    SYSC_AWO_CLK_SEL_PBUS0_POS = 20,
    SYSC_AWO_CLK_PBUS1_DIV4_MASK = (int)0x800000,
    SYSC_AWO_CLK_PBUS1_DIV4_POS = 23,
    SYSC_AWO_CLK_SEL_QSPI_MASK = (int)0x7000000,
    SYSC_AWO_CLK_SEL_QSPI_POS = 24,
    SYSC_AWO_CLK_FLT_SEL_MASK = (int)0x30000000,
    SYSC_AWO_CLK_FLT_SEL_POS = 28,
    SYSC_AWO_CLK_FLT_BYP_MASK = (int)0x40000000,
    SYSC_AWO_CLK_FLT_BYP_POS = 30,
};

enum SYSC_AWO_REG_PD_AWO_ANA2_FIELD
{
    SYSC_AWO_AWO_BG_RBIAS_TRIM_MASK = (int)0xf,
    SYSC_AWO_AWO_BG_RBIAS_TRIM_POS = 0,
};

enum SYSC_AWO_REG_PD_AWO_ANA0_FIELD
{
    SYSC_AWO_AWO_QCLK256M_SEL_MASK = (int)0x1,
    SYSC_AWO_AWO_QCLK256M_SEL_POS = 0,
    SYSC_AWO_AWO_EN_QCLK_MASK = (int)0x2,
    SYSC_AWO_AWO_EN_QCLK_POS = 1,
    SYSC_AWO_AWO_EN_DPLL_LOCK_BYPS_MASK = (int)0x4,
    SYSC_AWO_AWO_EN_DPLL_LOCK_BYPS_POS = 2,
    SYSC_AWO_AWO_EN_DPLL_128M_EXT_MASK = (int)0x8,
    SYSC_AWO_AWO_EN_DPLL_128M_EXT_POS = 3,
    SYSC_AWO_AWO_EN_DPLL_128M_RF_MASK = (int)0x10,
    SYSC_AWO_AWO_EN_DPLL_128M_RF_POS = 4,
    SYSC_AWO_AWO_EN_DPLL_16M_RF_MASK = (int)0x20,
    SYSC_AWO_AWO_EN_DPLL_16M_RF_POS = 5,
    SYSC_AWO_AWO_EN_DPLL_MASK = (int)0x40,
    SYSC_AWO_AWO_EN_DPLL_POS = 6,
    SYSC_AWO_AWO_ENB_DPLL_64M_EXT_MASK = (int)0x80,
    SYSC_AWO_AWO_ENB_DPLL_64M_EXT_POS = 7,
    SYSC_AWO_AWO_LVD_EN_MASK = (int)0x100,
    SYSC_AWO_AWO_LVD_EN_POS = 8,
    SYSC_AWO_AWO_LVD_REF_MASK = (int)0xe00,
    SYSC_AWO_AWO_LVD_REF_POS = 9,
    SYSC_AWO_AWO_LVD_CTL_MASK = (int)0x7000,
    SYSC_AWO_AWO_LVD_CTL_POS = 12,
    SYSC_AWO_AWO_LDO_DG_TRIM_MASK = (int)0x30000,
    SYSC_AWO_AWO_LDO_DG_TRIM_POS = 16,
    SYSC_AWO_AWO_DPLL_SEL_REF_24M_MASK = (int)0x40000,
    SYSC_AWO_AWO_DPLL_SEL_REF_24M_POS = 18,
    SYSC_AWO_AWO_DPLL_TESTEN_MASK = (int)0x80000,
    SYSC_AWO_AWO_DPLL_TESTEN_POS = 19,
    SYSC_AWO_AWO_BG_VREF_FINE_MASK = (int)0xc00000,
    SYSC_AWO_AWO_BG_VREF_FINE_POS = 22,
    SYSC_AWO_AWO_BG_RES_TRIM_MASK = (int)0x3f000000,
    SYSC_AWO_AWO_BG_RES_TRIM_POS = 24,
    SYSC_AWO_AWO_DPLL_VCO_ADJ_MASK = (int)0xc0000000,
    SYSC_AWO_AWO_DPLL_VCO_ADJ_POS = 30,
};

enum SYSC_AWO_REG_PD_AWO_ANA1_FIELD
{
    SYSC_AWO_AWO_RCO_MODE_SEL_MASK = (int)0x2000,
    SYSC_AWO_AWO_RCO_MODE_SEL_POS = 13,
    SYSC_AWO_AWO_RCO_CAL_START_MASK = (int)0x8000,
    SYSC_AWO_AWO_RCO_CAL_START_POS = 15,
    SYSC_AWO_AWO_EN_RCO_DIG_PWR_MASK = (int)0x10000,
    SYSC_AWO_AWO_EN_RCO_DIG_PWR_POS = 16,
    SYSC_AWO_AWO_ADC12B_DIG_PWR_EN_MASK = (int)0x20000,
    SYSC_AWO_AWO_ADC12B_DIG_PWR_EN_POS = 17,
    SYSC_AWO_AWO_OSCRC_DIG_PWR_EN_MASK = (int)0x40000,
    SYSC_AWO_AWO_OSCRC_DIG_PWR_EN_POS = 18,
    SYSC_AWO_AWO_XO32K_OE_BYPS_MASK = (int)0x100000,
    SYSC_AWO_AWO_XO32K_OE_BYPS_POS = 20,
    SYSC_AWO_AWO_XO32K_CODE_MASK = (int)0x200000,
    SYSC_AWO_AWO_XO32K_CODE_POS = 21,
    SYSC_AWO_AWO_XO16M_SEL_MASK = (int)0x400000,
    SYSC_AWO_AWO_XO16M_SEL_POS = 22,
    SYSC_AWO_AWO_XO16M_LP_MASK = (int)0x800000,
    SYSC_AWO_AWO_XO16M_LP_POS = 23,
    SYSC_AWO_AWO_XO16M_CAP_TRIM_MASK = (int)0x3f000000,
    SYSC_AWO_AWO_XO16M_CAP_TRIM_POS = 24,
    SYSC_AWO_AWO_XO16M_ADJ_MASK = (int)0xc0000000,
    SYSC_AWO_AWO_XO16M_ADJ_POS = 30,
};

enum SYSC_AWO_REG_MAC_SLP_INTR_FIELD
{
    SYSC_AWO_MAC_SLP_INTR_EN_MASK = (int)0x1,
    SYSC_AWO_MAC_SLP_INTR_EN_POS = 0,
    SYSC_AWO_MAC_SLP_INTR_CLR_MASK = (int)0x10,
    SYSC_AWO_MAC_SLP_INTR_CLR_POS = 4,
};

enum SYSC_AWO_REG_PIN_SEL0_FIELD
{
    SYSC_AWO_SWD_EN_MASK = (int)0x1,
    SYSC_AWO_SWD_EN_POS = 0,
    SYSC_AWO_SWV_EN_MASK = (int)0x2,
    SYSC_AWO_SWV_EN_POS = 1,
    SYSC_AWO_MDM_IO_EN_MASK = (int)0x4,
    SYSC_AWO_MDM_IO_EN_POS = 2,
    SYSC_AWO_CLK_HBUS_OUT_EN_MASK = (int)0x8,
    SYSC_AWO_CLK_HBUS_OUT_EN_POS = 3,
    SYSC_AWO_LCD_I8080_EN_MASK = (int)0x10,
    SYSC_AWO_LCD_I8080_EN_POS = 4,
    SYSC_AWO_HSE_OUT_EN_MASK = (int)0x20,
    SYSC_AWO_HSE_OUT_EN_POS = 5,
    SYSC_AWO_RF_IO_EN_MASK = (int)0x40,
    SYSC_AWO_RF_IO_EN_POS = 6,
    SYSC_AWO_BLE_SPI_EN_MASK = (int)0x80,
    SYSC_AWO_BLE_SPI_EN_POS = 7,
    SYSC_AWO_QSPI0_EN_MASK = (int)0x3f00,
    SYSC_AWO_QSPI0_EN_POS = 8,
    SYSC_AWO_MISC_DBG_EN_MASK = (int)0xff0000,
    SYSC_AWO_MISC_DBG_EN_POS = 16,
    SYSC_AWO_MISC_DBG_SEL_MASK = (int)0x3000000,
    SYSC_AWO_MISC_DBG_SEL_POS = 24,
    SYSC_AWO_CLK_OUT_SEL_MASK = (int)0x30000000,
    SYSC_AWO_CLK_OUT_SEL_POS = 28,
};

enum SYSC_AWO_REG_PIN_SEL1_FIELD
{
    SYSC_AWO_FUNC_IO_EN_L_MASK = (int)0xffffffff,
    SYSC_AWO_FUNC_IO_EN_L_POS = 0,
};

enum SYSC_AWO_REG_PIN_SEL2_FIELD
{
    SYSC_AWO_FUNC_IO_EN_H_MASK = (int)0x7ff,
    SYSC_AWO_FUNC_IO_EN_H_POS = 0,
};

enum SYSC_AWO_REG_PIN_SEL3_FIELD
{
    SYSC_AWO_MAC_DBG_EN_MASK = (int)0xffff,
    SYSC_AWO_MAC_DBG_EN_POS = 0,
    SYSC_AWO_MDM_DBG_EN_MASK = (int)0xffff0000,
    SYSC_AWO_MDM_DBG_EN_POS = 16,
};

enum SYSC_AWO_REG_IOA_LOCK_FIELD
{
    SYSC_AWO_GPIOA_LOCK_MASK = (int)0xffff,
    SYSC_AWO_GPIOA_LOCK_POS = 0,
};

enum SYSC_AWO_REG_IOA_OE_DOT_FIELD
{
    SYSC_AWO_GPIOA_DOT_MASK = (int)0xffff,
    SYSC_AWO_GPIOA_DOT_POS = 0,
    SYSC_AWO_GPIOA_OE_MASK = (int)0xffff0000,
    SYSC_AWO_GPIOA_OE_POS = 16,
};

enum SYSC_AWO_REG_IOA_PD_PU_FIELD
{
    SYSC_AWO_GPIOA_PU_MASK = (int)0xffff,
    SYSC_AWO_GPIOA_PU_POS = 0,
    SYSC_AWO_GPIOA_PD_MASK = (int)0xffff0000,
    SYSC_AWO_GPIOA_PD_POS = 16,
};

enum SYSC_AWO_REG_IOA_IE_OD_FIELD
{
    SYSC_AWO_GPIOA_OD_MASK = (int)0xffff,
    SYSC_AWO_GPIOA_OD_POS = 0,
    SYSC_AWO_GPIOA_IE_N_MASK = (int)0xffff0000,
    SYSC_AWO_GPIOA_IE_N_POS = 16,
};

enum SYSC_AWO_REG_IOA_DS_FIELD
{
    SYSC_AWO_GPIOA_DS2_MASK = (int)0xffff,
    SYSC_AWO_GPIOA_DS2_POS = 0,
    SYSC_AWO_GPIOA_DS1_MASK = (int)0xffff0000,
    SYSC_AWO_GPIOA_DS1_POS = 16,
};

enum SYSC_AWO_REG_IOA_AE_FIELD
{
    SYSC_AWO_GPIOA_AE2_MASK = (int)0xffff,
    SYSC_AWO_GPIOA_AE2_POS = 0,
    SYSC_AWO_GPIOA_AE1_MASK = (int)0xffff0000,
    SYSC_AWO_GPIOA_AE1_POS = 16,
};

enum SYSC_AWO_REG_IOA_FIR_FIELD
{
    SYSC_AWO_GPIOA_FIR_MASK = (int)0xffff,
    SYSC_AWO_GPIOA_FIR_POS = 0,
};

enum SYSC_AWO_REG_IOA_DIN_FIELD
{
    SYSC_AWO_GPIOA_DIN_MASK = (int)0xffff,
    SYSC_AWO_GPIOA_DIN_POS = 0,
};

enum SYSC_AWO_REG_IOB_LOCK_FIELD
{
    SYSC_AWO_GPIOB_LOCK_MASK = (int)0xffff,
    SYSC_AWO_GPIOB_LOCK_POS = 0,
};

enum SYSC_AWO_REG_IOB_OE_DOT_FIELD
{
    SYSC_AWO_GPIOB_DOT_MASK = (int)0xffff,
    SYSC_AWO_GPIOB_DOT_POS = 0,
    SYSC_AWO_GPIOB_OE_MASK = (int)0xffff0000,
    SYSC_AWO_GPIOB_OE_POS = 16,
};

enum SYSC_AWO_REG_IOB_PD_PU_FIELD
{
    SYSC_AWO_GPIOB_PU_MASK = (int)0xffff,
    SYSC_AWO_GPIOB_PU_POS = 0,
    SYSC_AWO_GPIOB_PD_MASK = (int)0xffff0000,
    SYSC_AWO_GPIOB_PD_POS = 16,
};

enum SYSC_AWO_REG_IOB_IE_OD_FIELD
{
    SYSC_AWO_GPIOB_OD_MASK = (int)0xffff,
    SYSC_AWO_GPIOB_OD_POS = 0,
    SYSC_AWO_GPIOB_IE_N_MASK = (int)0xffff0000,
    SYSC_AWO_GPIOB_IE_N_POS = 16,
};

enum SYSC_AWO_REG_IOB_DS_FIELD
{
    SYSC_AWO_GPIOB_DS2_MASK = (int)0xffff,
    SYSC_AWO_GPIOB_DS2_POS = 0,
    SYSC_AWO_GPIOB_DS1_MASK = (int)0xffff0000,
    SYSC_AWO_GPIOB_DS1_POS = 16,
};

enum SYSC_AWO_REG_IOB_AE_FIELD
{
    SYSC_AWO_GPIOB_AE2_MASK = (int)0xffff,
    SYSC_AWO_GPIOB_AE2_POS = 0,
    SYSC_AWO_GPIOB_AE1_MASK = (int)0xffff0000,
    SYSC_AWO_GPIOB_AE1_POS = 16,
};

enum SYSC_AWO_REG_IOB_FIR_FIELD
{
    SYSC_AWO_GPIOB_FIR_MASK = (int)0xffff,
    SYSC_AWO_GPIOB_FIR_POS = 0,
};

enum SYSC_AWO_REG_IOB_DIN_FIELD
{
    SYSC_AWO_GPIOB_DIN_MASK = (int)0xffff,
    SYSC_AWO_GPIOB_DIN_POS = 0,
};

enum SYSC_AWO_REG_IOC_LOCK_FIELD
{
    SYSC_AWO_GPIOC_LOCK_MASK = (int)0x7ff,
    SYSC_AWO_GPIOC_LOCK_POS = 0,
};

enum SYSC_AWO_REG_IOC_OE_DOT_FIELD
{
    SYSC_AWO_GPIOC_DOT_MASK = (int)0x7ff,
    SYSC_AWO_GPIOC_DOT_POS = 0,
    SYSC_AWO_GPIOC_OE_MASK = (int)0x7ff0000,
    SYSC_AWO_GPIOC_OE_POS = 16,
};

enum SYSC_AWO_REG_IOC_PD_PU_FIELD
{
    SYSC_AWO_GPIOC_PU_MASK = (int)0x7ff,
    SYSC_AWO_GPIOC_PU_POS = 0,
    SYSC_AWO_GPIOC_PD_MASK = (int)0x7ff0000,
    SYSC_AWO_GPIOC_PD_POS = 16,
};

enum SYSC_AWO_REG_IOC_IE_OD_FIELD
{
    SYSC_AWO_GPIOC_OD_MASK = (int)0x7ff,
    SYSC_AWO_GPIOC_OD_POS = 0,
    SYSC_AWO_GPIOC_IE_N_MASK = (int)0x7ff0000,
    SYSC_AWO_GPIOC_IE_N_POS = 16,
};

enum SYSC_AWO_REG_IOC_DS_FIELD
{
    SYSC_AWO_GPIOC_DS2_MASK = (int)0x7ff,
    SYSC_AWO_GPIOC_DS2_POS = 0,
    SYSC_AWO_GPIOC_DS1_MASK = (int)0x7ff0000,
    SYSC_AWO_GPIOC_DS1_POS = 16,
};

enum SYSC_AWO_REG_IOC_AE_FIELD
{
    SYSC_AWO_GPIOC_AE2_MASK = (int)0x7ff,
    SYSC_AWO_GPIOC_AE2_POS = 0,
    SYSC_AWO_GPIOC_AE1_MASK = (int)0x7ff0000,
    SYSC_AWO_GPIOC_AE1_POS = 16,
};

enum SYSC_AWO_REG_IOC_FIR_FIELD
{
    SYSC_AWO_GPIOC_FIR_MASK = (int)0x7ff,
    SYSC_AWO_GPIOC_FIR_POS = 0,
};

enum SYSC_AWO_REG_IOC_DIN_FIELD
{
    SYSC_AWO_GPIOC_DIN_MASK = (int)0x7ff,
    SYSC_AWO_GPIOC_DIN_POS = 0,
};

enum SYSC_AWO_REG_PWR_ACK_FIELD
{
    SYSC_AWO_PD_SEC_PWR_ACK_MASK = (int)0x1,
    SYSC_AWO_PD_SEC_PWR_ACK_POS = 0,
    SYSC_AWO_PD_BLE_PWR_ACK_MASK = (int)0x2,
    SYSC_AWO_PD_BLE_PWR_ACK_POS = 1,
    SYSC_AWO_PD_PER_PWR_ACK_MASK = (int)0x4,
    SYSC_AWO_PD_PER_PWR_ACK_POS = 2,
    SYSC_AWO_PD_SRAM_PWR_ACK_MASK = (int)0xf8,
    SYSC_AWO_PD_SRAM_PWR_ACK_POS = 3,
};

enum SYSC_AWO_REG_DBG_ACK_FIELD
{
    SYSC_AWO_CPU_CDBGPWRUPACK_MASK = (int)0x1,
    SYSC_AWO_CPU_CDBGPWRUPACK_POS = 0,
};

enum SYSC_AWO_REG_ANA_STAT_FIELD
{
    SYSC_AWO_BG_VREF_OK12_MASK = (int)0x1,
    SYSC_AWO_BG_VREF_OK12_POS = 0,
    SYSC_AWO_DPLL_LOCK_MASK = (int)0x2,
    SYSC_AWO_DPLL_LOCK_POS = 1,
};

#endif

